STUDENT

parents-scholarships
INTERNSHIPS
  • Kiran KB: IIIT, Delhi
  • Gaurav R Shenoy: Intel
  • Varsha V: Microsoft
  • Girish Bathala: Canon India
  • Namitha Nambiar: Aruba Networks, Hewlett Packard Enterprise
  • Nihal Sharma: IASc- INSA- NASI Summer Research Fellowship in 2016, IISc, Bangalore
FURTHER STUDIES
  • Subham Garodia, 99.41 percentile in CAT 2015
  • Shivani Kulakarni N, 95.25 percentile in CAT 2015
  • Bhagyashree Puranik, Ganesh Ramachandra Kini Securing admit in to M.E Communication System and Networking, IISc Bangalore

RESEARCH

PROJECTS

Saraswathy RM, Suma M, CH.V.Kartika DRDO, RADAR waveform generation using FPGA


Akshay Kumar C, Intel India, Bangalore, Design of Compensator for the LDOs


Raghuram B Hegde, Intel Mobile Communications, THREAD IP Stack Development


Zubin A Sunkad, IISc, Bangalore Speaker Biometrics


PAPERS IN JOURNALS AND CONFERENCES


CH.V.Kartika, Kavyashree C K,Saraswathy RM ICSNCS-2016


Akshay Kumar C IET-2015, ICACCI-15, ICKCE-2015, ICCCT-2015, ICECCS 2015


Chandana S 6th conference IEEE, ICCPCT 2016

workshopee

TEACHER

bdesfrontpage

Dr. T. S. Chandar: Reviewer: ACDOS – 2106, NIT, Trichy, Journal of Aerospace Science and Technology, Elsevier, Ph. D. External Examiner, Univ. of Pune.

Nagamani A N: Design of Reversible Floating Point Adder for DSP Applications, Design of Register File using Reversible Logic, An exact approach for complete test set generation of Toffoli-Fredkin and Peres based Reversible circuits

Dr Deepali Koppad: Low Power 1-bit full adder Circuit using Modified GDI, Conf. on Micro and Nano Technologies, Modelling and Simulation, Kuala Lumpur, Malaysia, Design and Comparison of Parallel prefix adders, Indo-Canadian. Symposium on Nano Science and Technology, Mysore

Dr Deepali Koppad, Dr.A.Srinivas, M. Rajasekar: Smart Mobile Kit, MSRIT, Bangalore

Jayashree H V: Ancilla-input and garbageoutput optim-ized design of a reversible quantum integer multiplier